The present invention relates to a method to fabricate high density dynamic random access memories (DRAMs). In specific, it relates to a method to fabricate such DRAMs having reduced bitline capacitance.
Both static random access memory (SRAM) and dynamic random access memory (DRAM) have one or more arrays of memory cells organized into rows (wordlines) and columns (bitlines). Each memory cell represents a single bit and is accessed by a unique address defined by the intersection of a row and a column. Reading data from or writing data to memory cells is achieved by activating selected wordlines and bitlines. In DRAMs, each input/output pin is connected to each memory cell via a xe2x80x9csense amplifierxe2x80x9d, which usually is one or more transistors configured to hold and amplify the charge to be read from or written to the cell. The sensitivity of the sense amplifier is proportional to the ratio of the capacitance of the node to the capacitance of the sensing bitline. Hence, it always is beneficial to have higher node capacitance or lower bitline capacitance (the bitline capacitance includes components of bitline to adjacent bitline, junction capacitance, and bitline to wordline capacitance).
As DRAMs are manufactured with increasing densities, the memory cells necessarily are made smaller and smaller and packed closer and closer together to pack as much memory into as small a space as possible. The increased density drives the bitlines closer together increasing the coupling between adjacent bitlines and also the coupling between bitlines and wordlines. This increased bitline capacitance makes it more difficult to detect the logical xe2x80x9c0xe2x80x9d or logical xe2x80x9c1xe2x80x9d in the memory cell.
Now, according to the present invention, a high density dynamic random access memory having substantially reduced bitline capacitance is provided, and, a method of fabricating such a DRAM device. This novel device is achieved mainly by reducing bitline contact to an active wordline capacitance. The proposed process offers advantages of (a) reduced aspect ratio of bitline etches, (b) reduced bitline to bitline leakage to thereby allow gap fills of lower reflow temperature, (c) reduced array junction leakage by utilizing a self-aligned polysilicon diffused junction for planar array transistors, and (d) improved support device rolloff characteristics due to use of raised source-drain junctions.